

module tb_top;
    // clock / reset
    logic clk;
    logic rst_n;

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end
    initial begin
        rst_n = 0;
        #20 rst_n = 1;
    end

    // instantiate interface instances
    aru_mul_cfg_if u_aru_cfg_if_inst1 ();  // 注意这里实例名可任意
    aru_payload_if u_aru_pld_top_if_inst1 ();
    aru_payload_if u_aru_pld_left_if_inst1 ();
    aru_payload_if u_aru_pld_right_if_inst1 ();
    aru_payload_if u_aru_pld_bottom_if_inst1 ();

    aru_max_min_cfg_if u_aru_cfg_if_inst2 ();  // 注意这里实例名可任意
    aru_payload_if u_aru_pld_top_if_inst2 ();
    aru_payload_if u_aru_pld_left_if_inst2 ();
    aru_payload_if u_aru_pld_right_if_inst2 ();
    aru_payload_if u_aru_pld_bottom_if_inst2 ();

    aru_div_cfg_if u_aru_cfg_if_inst3 ();  // 注意这里实例名可任意
    aru_payload_if u_aru_pld_top_if_inst3 ();
    aru_payload_if u_aru_pld_left_if_inst3 ();
    aru_payload_if u_aru_pld_right_if_inst3 ();
    aru_payload_if u_aru_pld_bottom_if_inst3 ();

    aru_add_sub_cfg_if u_aru_cfg_if_inst4 ();  // 注意这里实例名可任意
    aru_payload_if u_aru_pld_top_if_inst4 ();
    aru_payload_if u_aru_pld_left_if_inst4 ();
    aru_payload_if u_aru_pld_right_if_inst4 ();
    aru_payload_if u_aru_pld_bottom_if_inst4 ();



    // DUT 实例化：把 interface instance 传进去（匹配 modport 类型）
    aru_binary_mul dut1 (
        .clk                (clk),
        .rst_n              (rst_n),
        .u_aru_cfg_if       (u_aru_cfg_if_inst1),         // 连接接口实例
        .u_aru_pld_top_if   (u_aru_pld_top_if_inst1),
        .u_aru_pld_left_if  (u_aru_pld_left_if_inst1),
        .u_aru_pld_bottom_if(u_aru_pld_bottom_if_inst1),
        .u_aru_pld_right_if (u_aru_pld_right_if_inst1)
    );

    aru_binary_max_min dut2 (
        .clk                (clk),
        .rst_n              (rst_n),
        .u_aru_cfg_if       (u_aru_cfg_if_inst2),         // 连接接口实例
        .u_aru_pld_top_if   (u_aru_pld_top_if_inst2),
        .u_aru_pld_left_if  (u_aru_pld_left_if_inst2),
        .u_aru_pld_bottom_if(u_aru_pld_bottom_if_inst2),
        .u_aru_pld_right_if (u_aru_pld_right_if_inst2)
    );

    aru_binary_div dut3 (
        .clk                (clk),
        .rst_n              (rst_n),
        .u_aru_cfg_if       (u_aru_cfg_if_inst3),         // 连接接口实例
        .u_aru_pld_top_if   (u_aru_pld_top_if_inst3),
        .u_aru_pld_left_if  (u_aru_pld_left_if_inst3),
        .u_aru_pld_bottom_if(u_aru_pld_bottom_if_inst3),
        .u_aru_pld_right_if (u_aru_pld_right_if_inst3)
    );

    aru_binary_add_sub dut4 (
        .clk                (clk),
        .rst_n              (rst_n),
        .u_aru_cfg_if       (u_aru_cfg_if_inst4),         // 连接接口实例
        .u_aru_pld_top_if   (u_aru_pld_top_if_inst4),
        .u_aru_pld_left_if  (u_aru_pld_left_if_inst4),
        .u_aru_pld_bottom_if(u_aru_pld_bottom_if_inst4),
        .u_aru_pld_right_if (u_aru_pld_right_if_inst4)
    );

    // （可选）在 tb 里驱动接口信号，或在接口内写 driver/monitor task/class
    initial begin
        #1000 $finish;
    end
endmodule
